1. Field
The field of the invention relates to technology for implementing electronic design automation tools, and in particular, to design tools for performing timing aware via insertion.
2. Description of Related Art
An integrated circuit (IC) is a small electronic device typically formed from semiconductor material. Each IC contains a large number of electronic components, e.g., transistors, that are wired together to create a self-contained circuit device. The components and wiring on the IC are materialized as a set of geometric shapes that are placed and routed on the chip material. During placement, the location and positioning of each geometric shape corresponding to an IC component are identified on the IC layers. During routing, a set of routes are identified to tie together the geometric shapes for the electronic components.
Shrinking process technologies are encouraging chip designers to consider more constraints within the design flow that deal directly with manufacturing issues and increasing chip yields. While trying to increase the yield during design optimization, an important objective for the designer is to preserve the timing.
To enhance yield when processing chips at 130 nm and below, it is recommended to add wherever it is possible larger via structures, e.g., double vias and vias with extra metal enclosure, that are also known as “fat” vias.
There are many different ways to insert redundant vias. Some example approaches include: (i) on-wire mode; (ii) off-wire mode; and (iii) push-other-nets mode, which may be defined as pushing other wires to make more space to insert double vias. These three ways to insert redundant vias are illustrated in FIG. 1, which shows an electronic circuit without redundant vias 100 and the same electronic circuit with redundant vias 102. On-wire 110 redundant via insertion mode is the least disruptive regarding the timing, while off-wire 112 and on/off-wire with the push 114 of other nets can create some damage for the critical nets. In general, the last two methods 112, 114 affect chip timing and cause signal integrity issues, which can lead to functionality failure. The push operation 114 can be several levels deep and can move critical nets or place other wires too close inducing timing problems.
The optimization problem of inserting redundant vias with the respect of timing was addressed in the past in several ways. However, all methods in the past lacked the accuracy and control over final timing result.